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Trimsignal receives patent for dynamic frequency boosting exploiting path delay variability in ICs





IC Digital design development startup and intellectual property IP core licensee Trimsignal (www.trimsignal.com) has already been granted its first patent by the U.S. Patent and Trademark Office (USPTO) on its clever digital design clock boosting and dynamic clock selection hardware implementations and is on track to expand its global patent portfolio to no less than 45 US and foreign patents by the end of 2022.


The patent for “Dynamic Frequency Boosting Exploiting Path Delay Variability in Integrated Circuits”. The company develops intellectual property that when implemented in hardware can function as a virtual chip designed to fit inside an existing chip. This new chip is there to perform two new key functions: (i) Surveillance and (ii) Clock Scheduling.


Surveillance involves the monitoring of collecting and forwarding signal state status information from specific hardwired nodes (locations). The node positions are selected at the design phase on the basis of correlational parameters having to do with critical path variability.


Clock Scheduling describes the managing of the received signal state status information for the purpose of making an optimum clock rate determination.


The innovation lies in two respects. First, the selection of the clock rate of the existing chip must occur before the chip begins the processing of data down all possible variable length active paths. For this to occur, the surveillance and clock scheduling must be executed sufficiently in advance of the setting of the clock rate. Second, this execution must start in the immediately preceding cycle so the whole process is continuous. Taken literally, if the active longest paths in any given clocking cycle defines the worst case clock rate for that cycle, and the active longest paths over a series of three consecutive clock cycles during which data is being processed across the chip (assuming a single stage) is always different, it should be possible to set an ideal clock to match the active longest path timing requirements. In this case, the surveillance and clock scheduling will identify a different optimum clock for each cycle and set that clock to run at the end of the current clock, while the current clock is still running.


Why is this important?

ICs vary in price and quality in terms of performance, die area, and power. In computing, performance per watt (PPW) is a measure of the energy efficiency of computer hardware. Literally, it is the rate of computation that can be delivered by a computer for every watt of power consumed. By optimizing the existing chip clock rate as proposed, in a computationally intensive IC, the overall rate of computation (i.e., the speed by which the chip processes information) can be reduced significantly, which expressed in terms of performance translates into much higher overall performance, and in terms of PPW, better PPW.

For non-computationally intensive ICs, an IC designer optimizes a circuit design to work at the fastest frequency using the lowest possible voltage (Vref). In such a scenario, Trimsignal contemplates deploying Surveillance and Clock Scheduling in such a way so as to effectively allow the existing chip to operate at a lower Vref. It can do this, because short paths do not require long duty cycles, and maybe less prone to leakage issues. Voltage and Power have a squared (x2) relation. Hence, even a small change in voltage has an exponential effect on power savings. By selectively lowering the power and dynamically increasing frequency, Trimsignal can make certain types of ICs more power efficient over time.


The two scenarios, performance optimization & power optimization, are quite significant and valuable to chip manufacturers. This is because any flexibility to vary one’s IC production strategies (high, medium, low end chip product sets) to better match market needs and better satisfy customer demands without having to switch to a new process technology or go to a new generation chip design sooner rather than later, translates into tremendous cost savings and profits.

In ICs, with multiple chips (multi-core ICs), generally referred to as System-on-Chip solutions, there will be a variety of chips, some of which will benefit from a performance boost, some from a power savings, and some from a design strategy that is optimized for both power and performance.



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